All language subtitles for #01 Introduction to Verilog HDL using Free Software Icarus, GTKWave, and VS Code

hardware

description

language

is

a

computer

based

language

that

is

used

to

design

the

hardware

of

digital

or

analog

systems

in

textual

form

one

way

to

design

digital

systems

is

through

the

visual

approach

where

you

tried

to

put

neck

circuit

diagrams

using

wires

and

the

resulting

design

is

what

we

call

a

skimmer

ethic

diagram

however

when

circuit

complexity

increases

it

is

harder

to

design

the

circuit

using

schematic

diagrams

and

this

is

where

returned

to

textual

computer

language

that

concisely

captures

the

details

of

that

digital

design

the

key

advantage

of

you

seeing

eight

x

twelve

form

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designed

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a

standard

day

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each

the

l

or

hardware

description

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is

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you

pass

your

sirikit

designed

to

other

engineers

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designers

they

can

easily

understand

it

and

edit

it

in

an

efficient

manner

when

they

want

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your

circuit

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will

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change

a

few

lines

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goats

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wires

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are

some

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samples

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different

hardware

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hardware

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developed

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devices

r

cp

lds

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arrays

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f

b

g

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her

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description

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g

h

d

l

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circuits

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example

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can

group

logic

gates

into

java

objects

etc

etc

b

h

s

i

c

hardware

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v

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d

l

s

n

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signals

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designer

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circuit

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gate

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went

up

one

two

three

four

i'm

going

to

declared

that

deportes

a

be

here

are

in

boots

a

be

then

terminated

with

a

semi-colon

next

the

some

and

carry

here

that

will

be

passed

on

this

module

are

actually

output

ports

so

i'm

going

to

declare

them

i'm

going

to

tell

the

compiler

that

these

sports

are

used

as

output

ports

next

i'm

going

to

instantiate

some

gates

or

i'm

going

to

create

some

virtual

objects

for

the

gates

to

create

our

first

the

gate

which

is

an

ex

or

a

gate

i'll

type

in

x

or

and

then

the

name

of

this

gate

let's

just

named

this

as

x

one

so

what

i'm

doing

here

is

i

am

creating

a

virtual

object

of

your

the

gate

and

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name

of

that

gate

is

x

one

when

you

use

primitive

gates

the

first

argument

is

the

output

so

i'm

going

to

type

some

and

then

the

remaining

arguments

referred

to

input

so

the

inputs

for

x

one

based

on

this

diagram

the

inputs

are

a

and

be

so

i'm

going

to

terminate

this

with

a

semi

color

next

i'm

going

to

eight

or

instantiate

and

gate

with

a

name

a

one

so

i'm

going

to

type

and

for

an

gate

and

the

name

of

this

and

gate

is

a

one

we

are

naming

this

gates

because

sometimes

it

in

a

schematic

diagram

or

in

a

digital

silicate

you

have

multiple

gates

that's

why

it's

important

to

name

them

the

first

argument

our

first

set

of

arguments

should

refer

to

output

it's

in

our

case

the

output

of

this

a

one

gate

is

kerry

and

the

inputs

r

a

n

b

so

that's

it

we

already

created

the

module

or

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very

low

hdl

code

for

this

have

other

circuit

so

i'm

going

to

end

this

module

recalled

that

a

module

must

always

be

terminated

by

and

and

module

keyword

so

control

s

or

click

save

file

see

next

in

order

to

test

this

code

we

will

can

eat

a

test

bench

code

so

here

i'll

just

copy

this

file

copy

and

then

paste

it

in

the

same

folder

controlled

v

i'm

going

to

the

name

this

copy

us

the

same

name

as

the

module

but

at

the

end

i'm

going

to

include

underscores

the

be

which

denotes

that

this

is

that

best

bench

that

be

i'm

going

to

drag

this

and

drop

its

here

and

vs

code

i'm

going

to

delete

everything

so

for

demonstration

purposes

oh

just

include

a

comment

here

that

this

file

is

the

best

bench

for

half

other

that

the

and

this

is

saved

in

the

file

half

underscore

either

underscore

the

be

which

means

test

bench

that

be

so

in

our

class

we

use

this

naming

convention

that

if

you

want

to

create

a

test

bench

for

a

specific

module

you

just

named

that

test

bench

with

the

same

name

as

the

module

name

but

include

and

underscore

the

be

at

the

end

so

we

will

instantly

know

that

it

is

that

the

bench

and

not

a

regular

module

click

accent

then

include

space

the

filed

of

the

module

to

be

tested

which

is

half

underscore

either

that

the

so

when

you

have

this

accent

mark

here

for

example

accent

include

this

means

that

it

is

a

compiler

directive

meaning

to

see

you

will

execute

this

land

during

compile

time

and

during

compile

time

you're

actually

telling

the

compiler

that

you

have

to

include

the

country

sense

of

this

file

when

you

tried

to

compile

this

test

bench

next

we

will

again

and

close

the

code

for

our

test

bench

we

in

keyword

bear

module

and

module

i'm

just

going

to

pay

pierre

module

and

then

and

or

and

module

between

this

talk

keyword

bear

we

will

place

our

code

for

testing

this

half

other

circuits

so

let's

name

this

test

bench

as

half

underscore

either

underscored

the

be

and

since

this

doesn't

require

any

inputs

and

outputs

we

don't

have

to

include

any

sports

here

are

just

terminate

this

weird

semi-colon

in

this

test

bench

i

must

somehow

be

able

to

bury

the

values

of

the

inputs

so

to

do

that

i'm

going

to

type

here

reg

but

they're

not

that

a

n

b

r

inputs

according

to

some

reference

as

threads

means

registers

and

this

is

understandable

because

as

we

all

know

i

register

is

some

digital

element

that

can

store

a

binary

but

you

like

zero

or

one

registers

can

be

implemented

in

terms

of

flip

flops

or

an

array

of

flip

or

any

other

solid

state

components

and

as

we

all

know

and

body

the

value

of

register

so

dishes

and

an

appropriate

name

for

a

declaration

for

an

input

in

a

test

bench

next

if

we

want

to

declare

the

output

of

the

circuit

in

a

test

bench

we

use

the

keyword

wire

although

in

my

opinion

a

proper

name

for

this

declaration

is

a

because

when

you

have

approve

your

actually

measuring

a

signal

that

comes

from

the

outputs

of

ac

stem

so

in

my

opinion

broke

is

a

better

term

than

wire

but

then

again

in

very

log

when

you

want

to

tell

the

compiler

that

some

variables

are

used

as

output

you

declared

them

as

wires

so

again

the

outputs

here

are

some

and

carry

after

declaring

the

purpose

of

these

variables

which

we

will

pass

us

arguments

later

we

instantiate

or

image

of

to

be

tested

which

is

the

half

other

module

so

to

do

this

type

the

name

of

the

module

which

is

in

our

case

we

named

it

as

have

underscore

other

space

than

the

name

of

the

instance

for

example

add

one

then

we

pass

these

variables

a

be

salmon

carried

so

he

be

some

katie

if

this

is

an

actual

circuit

this

line

of

code

means

that

we

connect

this

that

sports

from

our

test

surrogate

to

the

parts

of

the

trial

half

other

circuit

so

i'm

going

to

terminate

this

statement

with

a

semi-colon

when

we

say

instantiate

were

actually

creating

a

ritual

objects

of

the

sirikit

in

the

memory

of

the

computer

next

week

and

eight

an

initial

block

and

the

code

inside

this

initial

beloved

is

executed

one

once

during

that

entire

simulation

since

we

have

a

small

surrogate

this

initial

block

is

enough

to

change

the

values

of

the

registered

inputs

if

i

only

have

one

statement

then

this

keyword

initial

does

not

need

to

include

begin

and

and

meaning

to

say

after

this

initial

keyword

and

notice

that

it

be

as

code

or

to

complete

this

initial

block

but

if

you

have

one

lane

of

statement

you

could

just

directly

insert

your

called

the

here

but

if

you

have

multiple

lines

of

code

inside

this

initial

block

then

you

have

to

enclose

this

with

a

begin

and

and

statement

so

for

example

begin

and

then

and

once

you're

entered

this

be

as

good

article

blitz

the

entire

block

so

inside

this

begin

and

and

block

we

will

insert

our

code

to

change

the

values

of

this

a

and

b

so

at

the

beginning

we

set

the

values

of

a

n

b

three

zero

equals

zero

and

then

be

it

was

zero

then

after

one

second

we

replace

their

value

swede

based

on

this

through

bull

zero

and

one

so

i'm

going

to

please

be

with

one

then

after

one

second

i'm

going

to

change

this

weird

one

zero

or

this

copied

this

beast

one

zero

and

then

after

one

second

i'll

change

the

value

to

a

equals

one

n

b

equals

one

so

when

you

ran

this

bench

apparently

the

registered

variable

see

or

a

n

b

will

have

different

values

but

in

order

to

view

the

timing

diagram

we

have

the

dump

the

saved

data

because

apparently

when

you

change

the

values

of

a

and

b

the

values

of

some

and

carry

will

also

change

a

swell

and

in

order

to

record

this

changes

were

going

to

dump

this

changes

in

this

variable

in

a

file

and

to

do

this

let's

try

to

put

it

inside

this

begin

black

also

let's

use

the

command

dollar

sign

dump

file

whatever

the

changes

are

in

this

module

we

will

save

these

changes

in

a

file

and

renamed

this

file

us

for

example

have

other

that

v

c

d

i'll

terminate

this

way

of

semi-colon

dollar

said

dump

file

is

a

command

used

to

dump

the

changes

in

the

values

of

the

registers

and

wires

in

a

file

whose

filename

depends

on

the

argument

for

example

in

our

case

we

just

named

israel

as

have

underscored

other

that

b

c

d

vc

demands

value

change

dumped

by

default

it

will

dump

all

the

changes

in

this

fight

but

if

we

want

to

control

which

variables

deceived

we

use

the

command

dollar

sign

dump

worse

it

has

two

arguments

the

level

and

the

module

name

or

variable

name

so

let's

just

put

zero

here

which

means

that

we

are

dumping

all

the

variables

of

the

module

and

other

variables

instantiated

by

this

top

level

module

no

the

top

level

module

that

i'm

going

to

indicate

the

here

is

the

module

have

other

db

so

that

we

can

save

the

changes

in

this

variables

the

argument

here

is

directly

read

as

a

string

so

i'm

going

to

drop

the

coat

and

then

i'm

going

to

terminate

this

with

a

semicolon

let's

save

this

file

controlled

s

or

click

file

dan

save

the

compiled

this

testbench

click

this

toggle

panel

here

to

displayed

the

terminal

notice

that

the

current

directory

or

the

default

directory

of

this

terminal

is

the

home

directory

of

the

current

user

of

this

operating

system

but

we

need

to

access

this

files

so

i'm

going

to

copy

the

current

location

of

this

bias

and

then

go

back

to

my

terminal

and

type

cd

which

means

changed

directory

and

then

pace

there

directory

of

our

files

so

i'll

click

enter

i'm

going

to

play

clear

just

to

remove

some

details

of

this

terminal

okay

now

i'm

currently

at

the

location

of

this

file

so

i

can

directly

compile

them

so

to

compile

them

i'll

type

i

very

long

space

minus

or

the

output

the

output

will

be

named

us

let's

just

name

it

us

have

either

underscore

the

be

but

this

time

it's

file

extension

will

be

that

the

bp

the

source

file

to

be

compiled

is

have

other

witches

are

testbench

underscored

the

be

that

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so

click

enter

so

when

i

returned

to

this

location

or

folder

not

this

that

that

bbb

file

is

created

next

i'm

going

to

simulate

this

bbb

file

using

the

v

vp

command

bbb

command

space

than

the

name

of

this

bbb

fire

which

is

half

other

underscored

the

v

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the

bp

click

enter

if

we

return

to

this

folder

notice

that

a

that

b

c

d

file

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created

so

this

that

vc

the

file

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the

dump

file

that

contains

the

changes

in

the

outputs

and

inputs

of

this

test

bench

so

to

view

the

timing

diagram

of

this

dump

file

open

g

t

k

leave

the

so

type

g

d

k

we've

and

the

terminal

and

hit

enter

and

we

now

have

this

are

user

interface

for

g

tiki

wave

so

to

view

this

dump

file

click

file

up

in

new

tab

and

then

click

the

that

b

c

the

file

then

click

ok

select

half

other

that

db

and

then

click

one

signal

from

this

dump

file

and

then

click

control

eighth

or

select

everything

and

then

click

insert

so

that

they

will

be

inserted

in

this

signal

spinal

and

now

the

timing

diagram

are

displayed

for

all

the

signals

coming

from

our

test

bench

so

if

i

click

in

the

middle

of

zero

to

one

second

so

the

initial

values

of

a

be

zero

based

on

our

through

table

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carry

and

some

must

be

zero

zero

and

this

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correct

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let

me

click

between

one

second

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second

and

the

value

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for

a

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b

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set

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according

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ball

the

carry

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our

have

other

circuit

must

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zero

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one

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our

very

low

hdl

called

this

consistent

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correct

and

clicking

between

two

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three

seconds

the

values

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n

b

are

said

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her

one

and

zero

and

based

on

the

simulation

the

resulting

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some

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zero

and

one

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consistent

with

our

throats

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ball

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finally

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beyond

three

second

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set

values

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a

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one

in

one

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on

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table

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values

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carry

and

some

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one

zero

and

if

we

tried

to

much

this

with

our

simulation

are

stimulation

is

correct

which

means

that

we

have

successfully

implemented

the

circuit

using

the

very

a

each

the

end

before

we

and

this

discussion

let's

look

at

another

sirikit

that

contains

multiple

gates

and

multiple

wires

so

easily

code

these

in

very

long

h

hdl

l

relabel

each

gates

and

at

least

components

for

example

really

build

the

first

or

a

gate

with

oh

one

the

first

gate

with

a

one

the

first

not

gate

with

n

one

the

second

or

gate

with

auto

and

the

second

and

gate

with

a

though

when

it

comes

to

the

wires

really

bow

this

wire

of

weird

w

one

the

second

why

are

we

w

to

the

third

wire

with

w

three

and

the

fort

why

readable

your

for

so

to

implement

it

in

very

low

hdl

i'm

going

to

copy

this

have

other

that

be

so

that

i

will

automatically

huh

have

a

very

log

file

and

just

rename

this

as

for

example

some

ball

underscores

circuit

get

then

i'm

going

to

drag

and

drop

this

on

our

be

as

code

i'm

going

to

delete

everything

so

to

implement

this

i'll

start

with

module

enter

and

let's

just

named

this

sirikit

as

some

paul

underscores

circuit

i'm

going

to

put

some

part

list

here

he

b

c

the

in

he

and

and

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why

i'm

going

to

terminate

this

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a

semi-colon

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enter

let's

declare

a

b

c

d

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ports

as

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b

c

the

he

lipstick

clear

why

as

output

and

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declared

these

wires

w

want

to

for

us

wire

next

let's

instantiate

the

first

or

a

gate

so

i'm

going

to

type

or

and

then

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name

of

the

our

gate

which

is

oh

one

and

it

has

an

output

of

w

one

and

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a

and

b

next

we

instantiate

the

first

and

gate

so

i'm

going

to

and

and

then

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name

of

the

and

gate

is

a

one

it

hasn't

outward

of

w

to

and

inputs

see

and

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next

less

instantiate

the

not

gate

so

i'm

going

to

type

not

space

the

name

of

the

not

this

and

one

the

output

of

n

one

s

w

three

and

it's

input

is

w

one

next

i'm

going

to

instantiate

the

second

or

a

gate

so

i'm

going

to

type

or

space

the

name

of

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obligate

is

auto

and

it's

output

is

w

for

and

it's

inputs

are

w

three

and

w

though

finally

am

going

to

instantiate

the

second

and

gate

so

i'm

going

to

type

and

space

eat

though

it's

output

is

why

and

it's

inputs

r

w

for

and

he

then

i'm

going

to

close

this

module

by

writing

and

modern

so

that

test

this

you're

going

to

repeat

the

same

process

that

they've

shown

your

earlier

and

that's

it

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updates

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you

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watching